The formation of trench-isolated semiconductor circuit architectures customarily entails the planarization of one or more layers of material (usually containing at least one layer of dielectric, such as oxide material) atop the semiconductor substrate. In a trench-isolated structure, the overlay may also contain a layer of polycrystalline semiconductor material (e.g. polysilicon in the case of a silicon-based process), that has been non-selectively deposited on an oxide layer atop the trench-patterned wafer. The polysilicon fills the oxide coated trenches and piles up to some thickness on the top surface of the structure.
In order to prevent the planarization step, which typically involves the use of a chemical etching slurry containing a polishing grit material, from removing the actual substrate material beneath the overlay being polished, it is common practice to form a protective polishing-stop layer, such as silicon nitride, on that portion of the substrate to be protected. In the case of a CMOS integrated circuit architecture, for example, the protective layer may be disposed atop a relatively thin (e.g. on the order of several hundred angstroms) gate oxide layer and extend over an adjacent surface area of the substrate in which device regions (source and drain regions) are to be formed.
In accordance with a process previously developed by the assignee of the present application, the trench mask may be comprised of a sacrificial oxide layer formed atop the nitride layer, thereby forming, together with the pad oxide therebeneath, a triple layer laminate. This multi-layer laminate is selectively masked by a photoresist overlay and then the individual layers of the laminate are successively etched so as to define a patterning mask for the trench geometry of the substrate. Unfortunately, the use of such a multi-layer mask to trench-process the wafer is complicated and imprecise.
For example, the substantial and uneven thickness of the sacrificial oxide layer atop the nitride does not make it possible to readily define the point at which the nitride becomes exposed during selective etching of the thick oxide. Consequently, it may be necessary to employ a pilot wafer simply to measure the manner in which the sacrificial oxide is etched. Similarly, because of the reduced thickness of the pad oxide (only several hundred angstroms), identifying when to terminate the nitride etch is inexact.
An additional complication is the fact that, after the trench dielectric (oxide) layer is non-selectively deposited on the trench-patterned substrate, so as to coat the sidewalls and bottom surface of the trench, an excessive amount of this trench dielectric oxide may be removed during a following etch-down. The etching away of an excessive amount of trench oxide at the top or `lip` of the trench may result in a substrate surface having poor step coverage after polysilicon deposition and subsequent planarization to expose the nitride `stop` layer. Thus, although the substrate-protecting nitride layer may satisfactorily perform its planarization stop function, because of the necessity of precisely etching (an uneven oxide overlay) down to and through the nitride in the course of patterning the triple layer trench mask, a poly-filled, trench-isolated substrate realized through the use of such a mask may contain anomalies in its surface, particularly in the vicinity of the edges of the trenches.